## Friday, 28 September 2012

### Getting to know simulation - Part10 - Multi-Step

So continue from previous session, inserting C2 1nF to kill oscillation gives you the stability but make your buffer damn slow. You can try out few value to see the optimum C2 value for highest speed and still gives you the best stability, instead of manually change the values and re-run Transient Simulation, there is something called “Multi-Step” analysis that let you sweep any parameter and plot the result.

1. Open up analysis and tick “Enable multi-step”
2. Click “Define…” button and key in the  info as below:
3.  Run the simulation and you get the plot shown – looking at 1pF, 10pF, 100pF, 1nF you see that the best capacitance value for performance is at 10pF. And now you have a complete buffer design for the application stated in Part1 :) .

## Saturday, 22 September 2012

### Getting to know simulation - Part9 - Fixing oscillation

1.       There are plenty of ways to resolve this, one way is to add a capacitor in parallel with feedback resistor R2. Let’s do this in the schematic and re-do the AC simulation. At this point of time, the value of C2 is arbitrary chosen to be 1nF, we will talk more about this in next session – any way the latest schematic becomes:
2.       Re-do the simulation for AC with simulation frequency up to 10MHz to see the new closure- you can see now that the rate of closure becomes 20dB / decade – indicating stability has achieved, let’s modify the schematic to re-do the transient
3.       To look at the end result of the fix in time domain, insert 1nF for the transient simulation file:

4.       Re-run of transient simulation shows that so we have solved the problem of oscillation – but the problem is that the output of the buffer takes 4ms to settle to the right value – too slow for our liking – this we will try to solve in next session.

## Friday, 14 September 2012

### Getting to know simulation - Part8 - Arranging bode plot for AC analysis

1.       The best way to do AC stability analysis to plot Aforw vs 1/beta, plot of 1/beta essentially is the inversion of the beta gain – which is input/output instead of output/input – so let’s reverse the bode plot  and rename the block as shown
2.       So now you can see that the 40dB per decade closure of Aforw and 1/beta is the cause for oscillation

## Friday, 7 September 2012

### Getting to know simulation - Part7 - Bode Plot from a buffer circuit (that oscillate)

Continue from last post, to solve the problem, we need to acknowledge that the buffer circuit is in fact a feedback loop
To identify which components belong to with block – refer to the blog
Let’s modify the schematic to perform bode plot analysis
1.       Ground non-inverting input – since op-amp input is already high impedance – any voltage source with series resistance is pretty much behaving just like a pure voltage source – for DC voltage source, it is always a AC ground.
2.       Place large inductor, infinite AC coupling capacitor and AC source, configure the AC source as below:
3.       Choose AC analysis:
4.       Your schematic should becomes:
5.       After simulation, you get
6.       But, how to interpret the plot?

## Sunday, 2 September 2012

### Getting to know simulation - Part6 - Practical circuit consideration

Continue from last simulation done in Part5, the simulation result shows that the circuit is too ideal – in practical PCB, there will be about 10pF of capacitance from op amp input pin to GND, let’s insert this capacitance as below:

Re-run the transient and get:

In this case, we caught the potential issue - oscillation – as to solve it, let’s do it in the next posts.